The present invention generally relates to methodologies for measuring transistors, and more specifically relates to a new methodology for measuring many more transistors on a given test area than a conventional methodology provides.
A conventional method to measure a transistor matrix is illustrated in FIG. 1. As shown, the methodology provides that a pad group 10 is used (as an example, FIG. 1 illustrates a 2×10 pad group). In the methodology, test structures 12 (i.e., transistors) are placed in empty spaces between the pads 14. Using a shared gate and source, one 2×10 pad group can bold up to 9 test structures (i.e., transistors).
One drawback of this methodology is the effective usable area for transistor measurement is very small compared to the total test structure area. For example, in the 2×10 pad group as illustrated in FIG. 1, the effective transistor area is only up to 0.6% of the total test structure area.